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1 features ? single-chip sound studio with typical applications including: ? wavetable synthesis, serial midi in & out, mpu-401 (uart) ? game-compatible synthesis with adlib interface ? effects: reverb and chorus ? directsound ? , direct3dsound ? accelerator with static buffer support ? interactive 3-d positioning ? four-channel surround ? four-band equalizer ? mixer high-quality wavetable synthesis ? 16-bit samples with up to 48 khz sampling rate ? internal computations on 28 bits, dac support up to 20 bits ? alternate loop, 24 db digital filter for each voice professional effects ? 13 delay lines for resonance-free stereo reverb four-band final equalizer allows dramatic sound presence improvement expandable ? minimum system: ATSAM9707 + 512k bytes of rom + 32k x 8 ram + dac ? maximum system: ATSAM9707 + 64m bytes of dram + codec + dac high performance ? risc structure for sound synthesis/processing ? cisc structure for host communication and housekeeping ? audio transfer at maximum 16-bit isa bus speed ? audio transfer in burst mode: removes dma-controlled transfer burden fully programmable ? firmware downloaded to memory at power-up. easy software upgrade. ? chip programming open to third-party software companies ? powerful programming and debugging tools: algorithm compiler, sound editor, assembler and source debugger. direct development from pc environment, no special emulator required top technology ? single low-frequency crystal operation and built-in pll minimize rfi ? 144-lead tqfp space-saving package pin and function compatible with atsam9407 with additional features for professional use: ? up to eight channels of audio-in ? improved digital mix levels and digital overflow handling ? improved tuning accuracy ? additional dsp micro-instructions and datapath for more efficient audio processing algorithm coding note: pin-to-pin replacement for atsam9407 requires 3.3v core supply v c3 . description the ATSAM9707 is a highly integrated sound processor studio that combines a spe- cialized high-performance risc-based digital signal processor (synthesis/dsp) and a general-purpose 16-bit cisc-based control processor on a single chip. an on-chip memory management unit (mmu) allows the synthesis/dsp and the control processor to share external rom and/or ram memory devices. an intelligent peripheral i/o interface function handles other i/o interfaces, such as the isa pc bus, the on-chip midi uart and the codec control interface, with minimum intervention from the con- trol processor. sound synthesis ATSAM9707 integrated sound studio rev. 1711b-drmsd?11/02
2 ATSAM9707 1711b?drmsd?11/02 pin description table 1. pins by function pin name pin count type function gnd 17 pwr power ground ? all gnd pins should be returned to digital ground. v c3 3 pwr core power +3.3v nominal (3v to 4.5v). all v c3 pins should be returned to +3.3v. v cc 15 pwr power +3v to +5.5v ? all v cc pins should be returned to +5v (or 3.3v in case of single 3.3v supply). d[15:0] 16 i/o 16-bit data bus to host processor. has enough driving power to drive isa pc bus directly (24 ma buffer). information on these pins is: - parallel midi (mpu-401 type applications) - adlib control (game sound-type emulation) - down-/upload of pcm data or application programs direct isa pc bus drive requires 5v v cc . cs 1 in chip select from host, active low wr 1 in write from host, active low rd 1 in read from host, active low a[1:0] 3 in selects one of eight internal registers - 0, 1: mpu-401 registers - 2, 3: 16-bit data (burst dma mode) - 4-7: game sound registers irq 1 tsout tri-state output pin. can be connected directly to host irq line (24 ma). sbhe 1 in bus high enable signal, active low. normally connected to gnd. i/o ready 1 out open drain output buffer (24 ma); driven low during 16-bit burst mode transfers to synchronize pc to the ATSAM9707 memory. i/o cs16 1 out open drain output buffer (24 ma); driven low during 16-bit burst mode transfers. indicates to host that a 16-bit i/o is in progress. reset 1 in master reset input, active low. schmitt trigger input. x1 x2 2 crystal connection. crystal frequency should be f s x256 (typ 11.2896 mhz). crystal frequency is internally multiplied by four to provide the ic master clock. x1 can also be used as external clock input (3.3v input). x2 cannot be used to drive external circuitry. dabd[1:0] 2 out two stereo serial audio data outputs (four audio channels). each output holds 64 bits (2 x 32) of serial data per frame. audio data has precision of up to 20 bits. dabd0 can hold additional control data (mute, a/d gain, d/a gain, etc.). clbd 1 out audio data bit clock; provides timing to dabd061. wsbd 1 out audio data word select. the timing of wsbd can be selected to be i2s or japanese compatible. daad 1 in stereo serial audio data input midi_in 1 in serial midi_in input midi_out 1 out serial midi_out output
3 ATSAM9707 1711b?drmsd?11/02 note: pin names with an overbar (ras for example) indicate that the signal is active low. wa[24:0] 25 out external memory address (rom/sram). up to 32m words (64m 8-bit samples). wd[15:0] 16 i/o pcm rom/sram/dram data rbs 1 out sram byte select: should be connected to the lower ram address when 8- bit wide sram is used. the type of ram (16 bits/8 bits) can be selected by program. wcs0 1 out pcm rom chip select, active low. wcs1 1 out sram chip select, active low. wwe 1 out sram/dram write enable, active low. timing compatible with simm dram early write feature. woe 1 out pcm rom/sram output enable, active low. boot 1 in active high, specifies that built-in cpu bootstrap should be used at power-up (case of dram connection only). dra[11:0] 12 out multiplex dram address: 9-, 10-, 11-, 12-bit multiplex addressing can be used (from 256k x 16- to 16m x 16-type configurations). ras 1 out dram row address strobe cas 1 out dram column address strobe p[3:0] 4 i/o general-purpose configurable i/o pins. p1 to p3 can be configured as three additional stereo serial audio data inputs, providing the daad with up to eight channels of audio-in. s[1:0] 2 out indicates type of external memory cycle. s1s0 = 01: idle or refresh, 00: synthesis access, 10: instruction fetch, 11: processor read/write run 1 out high when the synthesis is initialized. can be used as reset for an external device (codec). lft 1 ana pll low pass filter. should be connected to an external rc network test pin; should be returned to gnd. test[2:0] 3 in test pins; should be returned to gnd. pdwn 1 in power-down, active low. table 1. pins by function (continued) pin name pin count type function
4 ATSAM9707 1711b?drmsd?11/02 pinout figure 1. ATSAM9707 in 144-lead tqfp package vcc irq gnd i/o cs16 wd13 midi out wd14 dra0 dra1 wd15 gnd vcc gnd vc3 vc3 lft x2 x1 reset pdwn vcc gnd dra2 cra3 midi in run dra4 vc3 gnd vcc gnd d0 clbd vc3 d1 rbs gnd d11 vcc d10 wa18 wa17 a2 a1 gnd rd vcc wr wa16 wa15 wa14 wa13 wa12 wa11 wa10 a0 wa9 wa8 wa7 gnd d9 vcc d8 wa6 wa5 wa4 wa3 gnd d7 vcc d6 wa2 boot d2 vcc d3 gnd dra5 daad dra6 dabd0 dra7 dra8 dabd1 wsbd wwe wcs0 wcs1 woe vcc dra9 gnd p0 p1 p2 p3 test0 test1 test2 gnd dra10 wa0 dra11 vcc d4 gnd d5 wa1 wd12 d15 wd11 d14 wd10 s1 wd9 wd8 s0 vcc cs gnd wd7 wd6 wd5 wd4 wd3 i/o ready wd2 wd1 wd0 wa24 wa23 sbhe gnd gnd vcc wa22 ras cas wa21 wa20 d13 vc13 d12 wa19 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
5 ATSAM9707 1711b?drmsd?11/02 typical designs figure 2. lowest cost design architecture figure 3. typical design architecture dram 256k x 16 codec codec sram 32k x 8 ATSAM9707 ATSAM9707 rom 256k x 16 or - general midi-compliant wavetable synthesis - compatible reverb + chorus - wave play and record (one stereo channel) - game-compatible synthesis - 3-d effect - four-band equalizer dram 1m x 16 ATSAM9707 dac option codec - professional-quality general midi-compliant synthesis - sound extensions - additional top-quality drumsets and bass - compatible reverb + chorus - downloadable sounds - wave play and record up to eight stereo channels with interactive 3-d positioning - game-compatible synthesis - directsound tm static buffer support - 3-d effect - four-channel surround (option) - four-band equalizer - audio-in effects (reverb or echo)
6 ATSAM9707 1711b?drmsd?11/02 functional description figure 4. ic architecture synthesis/dsp engine the synthesis/dsp engine operates on a frame-timing basis with the frame subdivided into 64 process slots. each process is itself divided into 16 micro-instructions known as ?algorithms?. up to 32 synthesis/dsp algorithms can be stored on-chip in the alg ram memory, allowing the device to be programmed for a number of audio signal generation/processing applications. the synthesis/dsp engine is capable of generating 64 simultaneous voices using algorithms such as wavetable synthesis with interpolation, alternate loop and 24 db resonant filtering for each voice. slots may be linked together (ml ram) to allow implementation of more complex synthesis algorithms. a typical multimedia application will use half the capacity of the synthesis/dsp engine for syn- thesis, thus providing state-of-the-art 32-voice wavetable polyphony. the remaining processing power will be used for typical func tions such as reverberation, chorus, direct sound, surround effect, equalizer, etc. frequently accessed synthesis/dsp parameter data are stored into five banks of on-chip ram memory. sample data or delay lines, which are accessed relatively infrequently, are stored in external rom, sram or dram memory. the combination of localized micro-program mem- ory and localized parameter data allows micro-instructions to execute in 20 ns (50 mips). separate buses from each of the on-chip parameter ram memory banks allow highly parallel data movement to increase the effectiveness of each micro-instruction. with this architecture, a single micro-instruction can accomplish up to six simultaneous operations (add, multiply, load, store, etc.), providing a potential throughput of 300 million operations per second (mops). p16 processor 16-bit cisc processor core includes: 256 x 16 data ram 256 x 16 boot rom mmu memory management unit i/o functions including: contol/status midi uart timers codec data i/f host i/f fifo host i/f burst synthesis/dsp risc dsp core includes: 512 x 32 alg ram 128 x 28 ma1 ram 256 x 28 ma2 ram 256 x 28 mb ram 256 x 16 mx ram 256 x 12 my ram 64 x 13 ml ram codec rom sram dram midi isa bus
7 ATSAM9707 1711b?drmsd?11/02 p16 control processor and i/o functions the p16 control processor is a general-purpose 16-bit cisc processor core that runs from external memory. a boot/macro rom is included on-chip to accelerate commonly executed routines and to allow the use of ram-only dev ices for the external memory. the p16 also includes 256 words of local ram data memory. the p16 control processor writes to the parameter ram blocks within the synthesis/dsp core in order to control the synthesis process. in a typical application, the p16 control processor parses and interprets incoming commands from the midi uart or from the pc isa interface and then controls the synthesis/dsp by writing into the parameter ram banks in the dsp core. slowly changing synthesis functions, such as lfos, are implemented in the p16 control processor by periodically updating the dsp parameter ram variables. the p16 control processor interfaces with other peripheral devices, such as the system control and status registers, the on-chip midi uart, the on-chip timers and the isa pc interface, through specialized ?intelligent? peripheral i/o logic. this i/o logic automates many of the sys- tem i/o transfers to minimize the amount of overhead processing required from the p16. the isa pc interface is implemented using three address lines (a2, a1, a0), a chip select sig- nal, read-and-write strobes from the host and a 16-bit data bus (d[15:0]). the data bus can drive the pc bus directly (24 ma buffers). an external decoder (pal) or plug & play ic is required to map the 12-bit i/o addresses and aen from the pc into the three address lines and chip select from the ATSAM9707. the isa pc interface supports a byte-wide prim ary i/o interface, a byte-wide auxiliary inter- face and a 16-bit port dedicated to burst transfers. the primary i/o interface is normally used to implement a roland mpu-401 uart-mode com- patible interface. it is specified by address a[2:0] = 00x, address 000 being the data register and address 001 being the status/control registers. besides the standard two status bits of the mpu-401, two additional bits are provided to expand the mpu-401 protocol. the auxiliary interface is allocated the address range a[2:0] = 1xx. it is normally used to implement a game-compatible interface. address a[2:0] = 010 specifies a 16-bit i/o port. it is mainly used for burst audio transfers to/from the pc using very efficient pc instructions such as rep outsw or rep insw, which operate at maximum isa bus bandwidth. this port may also be used for fast program or sound bank uploads. memory management unit (mmu) the memory management unit (mmu) block allows external rom and/or ram memory resources to be shared between the synthesis/dsp and the p16 control processor. this allows a single device (i.e., dram) to serve as sample memory storage/delay lines for the synthesis/dsp and as program storage/data memory for the p16 control processor.
8 ATSAM9707 1711b?drmsd?11/02 absolute maximum ratings note: all voltages with respect to 0v, gnd = 0v recommended operating conditions note: when using 3.3v supply, care must be taken that voltage applied on any pin does not exceed v cc + 0.5v. table 2. absolute maximum ratings ambient temperature (power applied)...............-40c to + 85c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating condtions for extended periods may affect device reliability. storage temperature.......................................-65c to + 150c voltage on any pin (except x1)....................-0.5v to v cc + 0.5v voltage on x1 pin ..........................................-0.5v to v c3 + 0.5v v cc supply voltage..............................................-0.5v to + 6.5v v c3 supply voltage................................................-0.5v t0 +4.5v maximum i ol per i/o pin.....................................................10ma (except d[15:0], irq, i/o ready) maximum i ol d[15:0], irq, i/o ready..................................30ma table 3. recommended operating conditions symbol parameter/condition min typ max unit v cc supply voltage (1) 3 3.3/5.0 5.5 v v c3 supply voltage 3 3.3 4.5 v t a operating ambient temperature 0 70 c
9 ATSAM9707 1711b?drmsd?11/02 dc characteristics table 4. dc characteristics (t a = 25c, v c3 = 3.3v 10%) symbol parameter/condition v cc min typ max unit v il low-level input voltage 3.3 5.0 -0.5 -0.5 1.0 1.7 v v v ih high-level input voltage 3.3 5.0 2.3 3.3 3.8 5.5 v v v ol low-level output voltage d[15:0], irq, i/o ready: i ol = -24 ma others except lft: i ol = -3.2 ma 3.3 5.0 0.45 0.45 v v v oh high-level output voltage d[15:0], irq, i/o ready: i oh =10 ma others except lft: i oh = 0.8 ma 3.3 5.0 2.8 4.5 v v i cc power supply current (crystal freq. = 12 mhz) 3.3 5.0 70 25 90 35 ma ma power-down supply current 70 100 a
10 ATSAM9707 1711b?drmsd?11/02 timings all timing conditions: v cc = 5v, v c3 = 3.3v, t a = 25c, signals i/o ready, i/o cs16 , d[15:0] with 220 pull-up, 30 pf capacitance, signal irq with 470 pull-down, 30 pf capacitance, all other outputs except x2 and lft load capacitance = 30 pf. all timings refer to t ck , which is the internal master clock period. the internal master clock frequency is four times the frequency at pin x1. therefore, t ck = t xtal /4. the sampling rate is given by 1/(t ck x 1024). the maximum crystal frequency/clock frequency at x1 is 12.288 mhz (48 khz sampling rate). crystal frequency selection considerations there is a trade-off between the crystal frequency and the support of widely available external dram/rom components. table 5 allows selection of the best fit for a given application. using a 11.2896 mhz crystal allows the use of widely available drams (-6 type) with a cycle time (t rc ) of 100 ns and an ras access time of 60 ns, as well as widely available roms with 100 ns access time, while providing state-of-the-art 44.1 khz sampling rate. pc host interface timing figure 5. pc host interface timing diagram note: d[15:8] valid only if a[2:1] = 10 and sbhe = 0. table 5. crystal frequency selection considerations sample rate (khz) crystal (mhz) t ck (ns) rom 1a (ns) dram t rac (ns) dram t rc (ns) comment 48 12.288 20.35 92 72 92 maximum frequency 44.1 11.2896 22.14 101 80 101 recommended for current designs 37.5 9.60 26.04 120 95 120 31.25 8.00 31.25 146 116 146 cs rd i/o cs16 d[15:0] t avcs t cslrdl t csliocs t prd drh t rdhcsh t rdliorl t pior t iorhdv t rdldv t t cshiocs sbhe i/o ready a[2:0]
11 ATSAM9707 1711b?drmsd?11/02 figure 6. pc host interface write cycle note: d8 - d15 valid only if a2a1 = 10. notes: 1. sbhe is normally not used (grounded). 2. when data is already loaded into internal ATSAM9707 output register. in this case i/o ready will stay high during the read cycle. 3. i/o ready will go low only if the data is not ready to be loaded into/read from internal ATSAM9707 register. 128 t ck corre- sponds to a single worst-case situation. at f ck = 11.2896 mhz, i/o ready is likely never to go low when using standard isa bus timing. 4. i/o cs16 is asserted low by ATSAM9707 if a[2:1] = 10 to indicate fast 16-bit isa bus transfer to the pc. table 6. pc host interface timing parameters symbol parameter min typ max unit t avcs address valid to chip select low 0 ns t cslrdl chip select low to rd or sbhe low (1) 5ns t rdhcsh rd or sbhe high to cs high 5 ns t prd rd or sbhe pulse width 50 ns t rdlvd data out valid from rd or sbhe (2) 20 ns t drh data out hold from rd or sbhe 510ns t rdliorl i/o ready low from rd or sbhe (3) 010ns t pior i/o ready pulse width (3) 128 t ck t iorhdv i/o ready rising to data out valid (3) 0ns t csliocs i/o cs16 low from cs low (4) 020ns t cshiocs i/o cs16 high from cs high (4) 020ns t cslrwrl chip select low to wr low (3) 5ns t wrhcsh wr high to cs high 5 ns t pwr wr pulse width 50 t wrliorl i/o ready low from wr low (3) 128 t ck t iorhwrh i/o ready high to wr high (3) 5ns t dws write data setup time 10 ns t dwh write data hold time 0 ns a[2:0] cs wr i/o ready i/o cs16 d[15:0] t avcs t cslwrl t csliocs t pwr t wrhcsh t iorhwrh t wrliorl t pior t dws t dwh t cshiocs
12 ATSAM9707 1711b?drmsd?11/02 external dram timing figure 7. external dram read cycle figure 8. external dram write cycle (early write) figure 9. external dram refresh cycle (ras only) ras cas dra[11:0] woe wd[15:0] t rc t ras t rp t rcd t cas t crp t asr t rah t asc t cah t cac t off t rac ras cas dra[11:0] wwe t rc t ras t rp t rcd t cas t crp t wch t wcs t dh t ds t asr t rah t asc t cah wd[15:0] ras t rc t ras t rp t asr counter t rah dra[11:0]
13 ATSAM9707 1711b?drmsd?11/02 notes: 1. the multiplexed cas , ras addressing can support memory dram chips up to 16 mb as long as the number of row address lines and column address lines are identical. for example, device type 416c1200 is supported because it is a 1m x 16 organization with 10-bit row and 10-bit column. device type 416c1000 is not supported because it is a 1m x 16 organization with 12-bit row and 8-bit column. 2. the signal woe is normally not used for dram connection. it is represented only for reference purposes. 3. as ras only counter refresh method is employed, several banks of drams can be connected using simple external cas decoding. linear address lines (wax) can be used to select between dram banks. for example, a 1m x 32 simm module may be connected as two 1m x 16 banks, with cas0 and cas1 selections issued from cas and wa20. 4. during a whole dram cycle (from ras low to cas rising), wcs0 is asserted low. 5. the equivalence between multiplexed dram address lines dra[11:0] and the corresponding linear addressing w[23:0] is as follows: 6. to save dram power consumption, cas and ras are cycled only when necessary. therefore, depending on firmware loaded, total board power consumption may increase with synthesis processing traffic. table 7. external dram timing parameters symbol parameter min typ max unit t rc read/write/refresh cycle 5 x t ck - 5 6 x t ck + 5 ns t rac access time from ras 4 x t ck - 5 ns t cac access time from cas 4 x t ck - 5 ns t off cas high to output high-z 2 x t ck - 5 ns t rp ras precharge time 2 x t ck ns t ras ras pulse width 3 x t ck - 5 ns t cas cas pulse width 3 x t ck - 5 ns t rcd ras to cas delay time t ck - 5 t ck + 5 ns t crp cas to ras precharge time t ck - 5 ns t asr row address setup time t ck - 5 ns t rah row address hold time t ck /2 ns t asc column address setup time t ck /2 - 5 ns t cah column address hold time 3 x t ck ns t wcs write command setup time t ck ns t wch write command hold time 4 x t ck ns t ds write data setup time t ck ns t dh write data hold time 3 x t ck ns ? refresh counter average period (12-bit counter) 512 x t ck ns dra11 dra10 dra9 dra8 dra7 dra6 dra5 dra4 dra3 dra2 dra1 dra0 ras time wa22 wa20 wa18 wa8 wa7 wa6 wa5 wa4 wa3 wa2 wa1 wa0 cas time wa23 wa21 wa19 wa17 wa16 wa15 wa14 wa13 wa12 wa11 wa10 wa9
14 ATSAM9707 1711b?drmsd?11/02 external rom cycle timing figure 10. external rom read cycle wcs0 wa[24:0] woe wd[15:0] t csoe t rc t poe t oe t df t ace table 8. external rom cycle timing parameters symbol parameter min typ max unit t rc read cycle time 5 x t ck 6 x t ck ns t csoe chip select low/address valid to woe low 2 x t ck - 5 3 x t ck + 5 ns t poe output enable pulse width 3 x t ck ns t ace chip select/address access time 5 x t ck - 5 ns t oe output enable access time 3 x t ck - 5 ns t df chip select or woe high to input data high-z 0 2 x t ck - 5 ns
15 ATSAM9707 1711b?drmsd?11/02 external ram timing figure 11. 16-bit sram read cycle figure 12. 16-bit sram write cycle wcs1 wa[24:0] wwe woe wd[15:0] t csoe t rc t poe t oe t df t ace wcs1 wa[24:0] wwe woe wd[15:0] t cswe t dh t dw t wp wc
16 ATSAM9707 1711b?drmsd?11/02 figure 13. 8-bit sram read cycle table 9. 16-bit sram timing parameters symbol parameter min typ max unit t rc read cycle time 5 x t ck 6 x t ck ns t csoe chip select low/address valid to woe low 2 x t ck - 5 3 x t ck + 5 ns t poe output enable pulse width 3 x t ck ns t ace chip select/address access time 5 x t ck - 5 ns t oe output enable access time 3 x t ck - 5 ns t df chip select or woe high to input data high-z 0 2 x t ck - 5 ns t wc write cycle time 5 x t ck 6 x t ck ns t cswe write enable low from cs or address or woe 2 x t ck - 10 ns t wp write pulse width 4 x t ck ns t dw data out setup time 4 x t ck - 10 ns t dh data out hold time 10 ns wcs1 wa[24:0] rbs wwe woe wd[7:0] t csoe t rc t orb t poe t oe t ach t df t ace high low
17 ATSAM9707 1711b?drmsd?11/02 figure 14. 8-bit sram write cycle low t dw1 wcs1 high rbs wwe woe t cswe t dw2 t wc t wp t wp t dh2 t dh1 t as wd[7:0] wa[24:0] table 10. 8-bit sram timing parameters symbol parameter min typ max unit t rc word read cycle time 5 x t ck 6 x t ck ns t csoe chip select low/address valid to woe low 2 x t ck - 5 3 x t ck + 5 ns t poe output enable pulse width 3 x t ck ns t ace chip select/address low byte access time 3 x t ck - 5 ns t oe output enable low byte access time t ck - 5 ns t orb output enable low to byte select high t ck ns t ach byte select high byte access time 2 x t ck - 5 ns t df chip select or woe high to input data high-z 0 2 x t ck - 5 ns t wc word write cycle time 5 x t ck 6 x t ck ns t cswe first wwe low from cs or address or woe 2 x t ck - 10 ns t wp write (low and high byte) pulse width 1.5 x t ck - 5 ns t dw1 data out low byte setup time 1.5 x t ck - 10 ns t dh1 data out low byte hold time 0.5 x t ck + 10 ns t as rbs high to second write pulse 0.5 x t ck - 5 ns t dw2 data out high byte setup time 2 x t ck - 10 ns t dh2 data out high byte hold time 10 ns
18 ATSAM9707 1711b?drmsd?11/02 digital audio timing figure 15. digital audio timing figure 16. digital audio frame format notes: 1. selection between i2s and japanese format is a firmware option. 2. daad is 16 bits only. 3. when connected with codecs such as cs4216 or cs4218, d[11:0] can be used to hold independent auxiliary information on left and right words. refer to corresponding codec datasheets for details. wsbd clbd dabd0 dabd1 daad t cw t cw t clbd t sod t sod table 11. digital audio timing parameters symbol parameter min typ max unit t wc clbd rising to wsbd change 8 x t ck - 10 ns t sod dabd valid before/after clbd rising 8 x t ck - 10 ns t clbd clbd cycle time 16 x t ck ns msb msb lsb (16 bits) lsb (18 bits) lsb (20 bits) wsbd (i2s) wsbd (japanese) clbd d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 dabd0 dabd1 daad (1) (2) (3) (1)
19 ATSAM9707 1711b?drmsd?11/02 reset and power-down during power-up, the reset input should be held low until the crystal oscillator and pll are stabilized, which can take about 20 ms. the reset signal is normally derived from the pc master reset. however, a typical rc/diode power-up network can also be used for some applications. after the low-to-high transition of reset , the following occurs: the synthesis/dsp enters an idle state, executing ras only refresh cycles. the run output is set to zero. if boot is low, then p16 program execution starts from address 0100h in rom space (wcs0 low). if boot is high, then p16 program execution starts from address 0000h in internal bootstrap rom space. the internal bootstrap expects to receive 256 words from the 16-bit burst transfer port, which will be stored from 0100h to 01ffh into the external dram space. the bootstrap then resumes control at address 0100h. if pdwn is asserted low, then all i/os and outputs will be floated and the crystal oscillator and pll will be stopped. the chip enters a deep power-down sleep mode. to exit power- down, pdwn has to be asserted high, then reset applied. recommended board layout like all hcmos high-integration ics, the following simple rules of board layout are mandatory for reliable chip operation: gnd, v cc , v c3 distribution, decouplings all gnd, v cc , v c3 pins should be connected. gnd and v cc planes are strongly recommended below the ATSAM9707. the board gnd and v cc distribution should be in grid form. if 3.3v supply is not available, then v c3 can be derived from v cc by two 1n4148 diodes in series. recommended decoupling is 0.1 f at each corner of the ic with an additional 10 f decou- pling close to the crystal. v c3 requires a single 0.1 f decoupling close to the ic. crystal, lft the paths between the crystal, the crystal compensation capacitors, the lft filter r-c-r and the ATSAM9707 should be short and shielded. the ground return from the compensation capacitors and lft filter should be the gnd plane from ATSAM9707. buses parallel layout from d[15:0] and dra[11:0]/w d[15:0] should be avoided. the d[15:0] bus is an asynchronous, high-transient, current-type bus. even on short distances, it can induce pulses on dra[11:0]/wd[15:0], which can corrupt address and/or data on these buses. a ground plane should be implemented below the d[15:0] bus, which connects to the pc-isa connector and to the ATSAM9707 gnd. a ground plane should be implemented below the dra[11:0]/wd[15:0] bus, which connects to the dram simm grounds and to the ATSAM9707. analog section a specific agnd ground plane that connects by a single trace to the gnd ground should be provided. no digital signals should cross the agnd plane. refer to the codec vendor-recom- mended layout for correct implementation of the analog section.
20 ATSAM9707 1711b?drmsd?11/02 recommended crystal compensation and lft filter figure 17. recommended crystal compensation and lft filter description r1 100 ? c2 2.2 nf c3 10 nf x1 x1 x2 lft pdwn v cc run c4 22 pf c1 22 pf 19 18 17 16 37 20 boot reset 26
21 ATSAM9707 1711b?drmsd?11/02 mechanical dimensions figure 18. 144-lead thin plastic lead quad flat pack table 12. package dimensions (in mm) dimension min typ max a 1.40 1.50 1.60 a1 0.05 0.10 0.15 a2 1.35 1.40 1.45 d 21.90 22.00 22.10 d1 19.90 20.00 20.10 e 21.90 22.00 22.10 e1 19.90 20.00 20.10 l 0.45 0.60 0.75 p0.50 b 0.17 0.22 0.27
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